From 3e872edc5706b1144016ef9352521f16b23f57b2 Mon Sep 17 00:00:00 2001 From: liu shiwei Date: Wed, 16 Sep 2026 13:36:41 +0800 Subject: [PATCH 2/3] =?utf-8?q?iflyhome-i01=20=E5=A2=9E=E5=8A=A0=20uboot?= =?utf-8?q?=20rk3328=E7=9A=84=E4=B8=B2=E5=8F=A3=E6=97=B6=E9=92=9F=E6=98=AF?= =?utf-8?q?75Mhz,=20=E4=B8=8D=E6=98=AF=E5=A4=96=E7=BD=AE=E6=99=B6=E6=8C=AF?= =?utf-8?q?24Mhz?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit --- package/boot/uboot-rockchip/Makefile | 8 + .../patches/999-uboot_iflyhome_i01.patch | 567 ++++++++++++++++++ 2 files changed, 575 insertions(+) create mode 100644 package/boot/uboot-rockchip/patches/999-uboot_iflyhome_i01.patch diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index cfe3907470..ec8c8e0455 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -99,6 +99,13 @@ define U-Boot/rock64-rk3328 pine64_rock64 endef +define U-Boot/iflyhome-i01-rk3328 + $(U-Boot/rk3328/Default) + NAME:=iFLYHOME I01 + BUILD_DEVICES:= \ + iflyhome_i01 +endef + define U-Boot/rock-pi-e-rk3328 $(U-Boot/rk3328/Default) NAME:=ROCK Pi E @@ -425,6 +432,7 @@ UBOOT_TARGETS := \ orangepi-r1-plus-lts-rk3328 \ roc-cc-rk3328 \ rock64-rk3328 \ + iflyhome-i01-rk3328 \ rock-pi-e-rk3328 \ rock-pi-e-v3-rk3328 \ hinlink-h28k-rk3528 \ diff --git a/package/boot/uboot-rockchip/patches/999-uboot_iflyhome_i01.patch b/package/boot/uboot-rockchip/patches/999-uboot_iflyhome_i01.patch new file mode 100644 index 0000000000..2fc9a8d17b --- /dev/null +++ b/package/boot/uboot-rockchip/patches/999-uboot_iflyhome_i01.patch @@ -0,0 +1,567 @@ +diff -uNra a/arch/arm/dts/rk3328-iflyhome-i01-u-boot.dtsi b/arch/arm/dts/rk3328-iflyhome-i01-u-boot.dtsi +--- a/arch/arm/dts/rk3328-iflyhome-i01-u-boot.dtsi 1970-01-01 08:00:00.000000000 +0800 ++++ b/arch/arm/dts/rk3328-iflyhome-i01-u-boot.dtsi 2026-09-20 15:41:01.972102157 +0800 +@@ -0,0 +1,71 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd ++ */ ++ ++#include "rk3328-u-boot.dtsi" ++#include "rk3328-sdram-ddr3-666.dtsi" ++ ++/ { ++ smbios { ++ compatible = "u-boot,sysinfo-smbios"; ++ ++ smbios { ++ system { ++ manufacturer = "iFLYTEK"; ++ product = "iflyhome-i01_rk3328"; ++ }; ++ ++ baseboard { ++ manufacturer = "iFLYTEK"; ++ product = "iflyhome-i01_rk3328"; ++ }; ++ ++ chassis { ++ manufacturer = "iFLYTEK"; ++ product = "iflyhome-i01_rk3328"; ++ }; ++ }; ++ }; ++}; ++ ++&spi0 { ++ flash@0 { ++ bootph-pre-ram; ++ bootph-some-ram; ++ }; ++}; ++ ++&spi0m2_clk { ++ bootph-pre-ram; ++ bootph-some-ram; ++}; ++ ++&spi0m2_cs0 { ++ bootph-pre-ram; ++ bootph-some-ram; ++}; ++ ++&spi0m2_rx { ++ bootph-pre-ram; ++ bootph-some-ram; ++}; ++ ++&spi0m2_tx { ++ bootph-pre-ram; ++ bootph-some-ram; ++}; ++ ++&usb20_otg { ++ hnp-srp-disable; ++}; ++ ++&uart1 { ++ bootph-all; ++ clock-frequency = <75000000>; ++}; ++ ++&uart1_xfer { ++ bootph-pre-sram; ++ bootph-pre-ram; ++}; +diff -uNra a/configs/iflyhome-i01-rk3328_defconfig b/configs/iflyhome-i01-rk3328_defconfig +--- a/configs/iflyhome-i01-rk3328_defconfig 1970-01-01 08:00:00.000000000 +0800 ++++ b/configs/iflyhome-i01-rk3328_defconfig 2026-09-20 14:44:08.830073626 +0800 +@@ -0,0 +1,109 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SPL_GPIO=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SF_DEFAULT_SPEED=20000000 ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-iflyhome-i01" ++CONFIG_BOOTARGS="console=ttyS1,115200n8" ++CONFIG_DM_RESET=y ++CONFIG_ROCKCHIP_RK3328=y ++CONFIG_ROCKCHIP_SPI_IMAGE=y ++CONFIG_SYS_LOAD_ADDR=0x800800 ++CONFIG_DEBUG_UART_BASE=0xFF120000 ++CONFIG_DEBUG_UART_CLOCK=75000000 ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_SPL_SPI=y ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_FIT_SIGNATURE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-iflyhome-i01.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_POWER=y ++CONFIG_SPL_SPI_LOAD=y ++CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 ++CONFIG_SPL_ATF=y ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_POWEROFF=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_CMD_REGULATOR=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_TPL_OF_CONTROL=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_TPL_OF_PLATDATA=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_ENV_RELOC_GD_ENV_ADDR=y ++CONFIG_ENV_MMC_DEVICE_INDEX=1 ++CONFIG_TPL_DM=y ++CONFIG_SPL_DM_SEQ_ALIAS=y ++CONFIG_REGMAP=y ++CONFIG_SPL_REGMAP=y ++CONFIG_TPL_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_SPL_SYSCON=y ++CONFIG_TPL_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_SPI_FLASH_SFDP_SUPPORT=y ++CONFIG_SPI_FLASH_GIGADEVICE=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_WINBOND=y ++CONFIG_SPI_FLASH_XTX=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DM_ETH_PHY=y ++CONFIG_PHY_GIGE=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PINCTRL=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM=y ++CONFIG_SPL_RAM=y ++CONFIG_TPL_RAM=y ++CONFIG_DM_RNG=y ++CONFIG_RNG_ROCKCHIP=y ++CONFIG_BAUDRATE=115200 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_ROCKCHIP_SPI=y ++CONFIG_SYSINFO=y ++CONFIG_SYSINFO_SMBIOS=y ++CONFIG_SYSRESET=y ++# CONFIG_TPL_SYSRESET is not set ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC2=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_TPL_TINY_MEMSET=y ++CONFIG_ERRNO_STR=y +diff -uNra a/dts/upstream/src/arm64/rockchip/rk3328-iflyhome-i01.dts b/dts/upstream/src/arm64/rockchip/rk3328-iflyhome-i01.dts +--- a/dts/upstream/src/arm64/rockchip/rk3328-iflyhome-i01.dts 1970-01-01 08:00:00.000000000 +0800 ++++ b/dts/upstream/src/arm64/rockchip/rk3328-iflyhome-i01.dts 2026-09-20 14:52:59.105648166 +0800 +@@ -0,0 +1,375 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * iFLYHOME i01 - RK3328 ++ * ++ * First mainline/OpenWrt bring-up DTS. ++ * Reconstructed from the original Rockchip 3.10 BSP DTB and compared with ++ * mainline rk3328-rock64.dts / rk3328-roc.dtsi. ++ * ++ * Known board facts from vendor DT: ++ * - RK3328 ++ * - RK805 @ I2C1 / 0x18 ++ * - eMMC on ff520000, 8-bit, HS200 capable ++ * - RTL8822CS Wi-Fi on ff500000 (mainline label: &sdmmc) ++ * - RTL8822CS BT on UART2 (ff130000), enable GPIO1_D0 ++ * - debug console on UART1 (ff120000) ++ * - GMAC2IO RGMII, external 125 MHz clock ++ * - PHY reset GPIO2_A3, tx_delay 0x26, rx_delay 0x20 ++ * - LEDs GPIO0_A2 / GPIO0_A0 ++ * - power key GPIO1_D2 ++ * ++ * Keep the first boot conservative: audio, HDMI and IR are not enabled here. ++ */ ++ ++/dts-v1/; ++ ++#include "rk3328.dtsi" ++#include ++ ++/ { ++ model = "iFLYHOME i01"; ++ compatible = "iflyhome,i01", "rockchip,rk3328"; ++ ++ aliases { ++ ethernet0 = &gmac2io; ++ mmc0 = &emmc; ++ mmc1 = &sdmmc; /* RTL8822CS SDIO, despite the mainline label name */ ++ }; ++ ++ chosen { ++ /* Vendor BSP debug output uses UART1 @ ff120000. */ ++ stdout-path = "serial1:115200n8"; ++ }; ++ ++ gmac_clkin: external-gmac-clock { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <125000000>; ++ clock-output-names = "gmac_clkin"; ++ }; ++ ++ vcc_sys: regulator-vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ /* ++ * Vendor property WIFI,poweren_gpio = GPIO1_C2, active high. ++ * mmc-pwrseq-simple models that line as an active-low reset: asserted LOW, ++ * released HIGH. This gives the same electrical power-enable behaviour. ++ */ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ post-power-on-delay-ms = <200>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led_work: led-0 { ++ label = "i01:work"; ++ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ ++ led_standby: led-1 { ++ label = "i01:standby"; ++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ key-power { ++ label = "Power"; ++ linux,code = ; ++ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_LOW>; ++ wakeup-source; ++ }; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++/* Samsung eMMC: vendor BSP enables 8-bit, DDR and HS200. */ ++&emmc { ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; ++ vmmc-supply = <&vcc_io>; ++ vqmmc-supply = <&vcc18_emmc>; ++ status = "okay"; ++}; ++ ++/* ++ * IMPORTANT: ++ * Vendor BSP: rksdmmc@ff500000 is the RTL8822CS Wi-Fi bus. ++ * Mainline rk3328.dtsi calls ff500000 "sdmmc", not "sdio". ++ */ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sdio-irq; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4>; ++ keep-power-in-suspend; ++ non-removable; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ max-frequency = <150000000>; ++ vqmmc-supply = <&vdd_18>; /* vendor sdio_vref = 1800 mV */ ++ status = "okay"; ++}; ++ ++/* ff510000 was disabled in the vendor DT; keep it disabled. */ ++&sdio { ++ status = "disabled"; ++}; ++ ++&gmac2io { ++ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; ++ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; ++ clock_in_out = "input"; ++ phy-mode = "rgmii"; ++ phy-supply = <&vcc_io>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmiim1_pins>; ++ ++ /* Vendor BSP values -- do not replace with ROCK64 GPIO/delays. */ ++ snps,reset-gpio = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++ tx_delay = <0x26>; ++ rx_delay = <0x20>; ++ ++ status = "okay"; ++}; ++ ++/* RK805 is physically connected to I2C1 @ ff160000. */ ++&i2c1 { ++ status = "okay"; ++ ++ rk805: pmic@18 { ++ compatible = "rockchip,rk805"; ++ reg = <0x18>; ++ ++ /* ++ * Vendor 3.10 RK805 gpios: ++ * pmic_int = GPIO2_D2 ++ * pmic_sleep = GPIO2_C6 ++ * RK805 INT is active low in mainline. ++ */ ++ interrupt-parent = <&gpio2>; ++ interrupts = ; ++ ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk805-clkout2"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc5-supply = <&vcc_io>; ++ vcc6-supply = <&vcc_sys>; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-min-microvolt = <700000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <12500>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1150000>; ++ }; ++ }; ++ ++ vdd_arm: DCDC_REG2 { ++ regulator-name = "vdd_arm"; ++ regulator-min-microvolt = <700000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <12500>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1150000>; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_io: DCDC_REG4 { ++ regulator-name = "vcc_io"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vdd_18: LDO_REG1 { ++ regulator-name = "vdd_18"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc18_emmc: LDO_REG2 { ++ regulator-name = "vcc18_emmc"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ /* Vendor board uses 1.1 V here, not ROCK64/ROC-CC's 1.0 V. */ ++ vdd_11: LDO_REG3 { ++ regulator-name = "vdd_11"; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1100000>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&io_domains { ++ status = "okay"; ++ vccio1-supply = <&vcc_io>; ++ vccio2-supply = <&vcc18_emmc>; ++ vccio3-supply = <&vcc18_emmc>; ++ vccio4-supply = <&vdd_18>; ++ vccio5-supply = <&vcc_io>; ++ vccio6-supply = <&vcc_io>; ++ pmuio-supply = <&vcc_io>; ++}; ++ ++&pinctrl { ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ /* Vendor RK805 pmic_sleep = GPIO2_C6; retained for later suspend/poweroff work. */ ++ pmic_sleep_l: pmic-sleep-l { ++ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++/* Existing physical debug console. */ ++&uart1 { ++ status = "okay"; ++}; ++ ++/* ++ * Vendor BSP leaves UART2 enabled and uses a separate bluetooth-platdata node. ++ * On this board it is very likely the RTL8822CS Bluetooth UART. ++ */ ++&uart2 { ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "realtek,rtl8822cs-bt"; ++ enable-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; ++ max-speed = <1500000>; ++ }; ++}; ++ ++&tsadc { ++ status = "okay"; ++}; ++ ++&u2phy { ++ status = "okay"; ++}; ++ ++&u2phy_host { ++ status = "okay"; ++}; ++ ++&u2phy_otg { ++ status = "okay"; ++}; ++ ++&usb20_otg { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usbdrd3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; -- 2.47.3